BigInt ratio math

PLL Divider And Rational Ratio Calculator

Designed for clock trees, audio sample rates, UART baud rates, and divider setup. Fraction reduction uses BigInt to avoid silent integer precision loss.

Inputs

Local

Source clock MHz Target clock MHz Maximum denominator

Ready. All processing runs locally in this browser.

Output

Offline

Practical guide

PLL Divider / Rational Ratio Calculator

Find practical numerator and denominator pairs for clocks, baud rates, sample rates, and divider configuration.

How to use

Enter the source clock and target clock in MHz.
Set a maximum denominator that matches the divider range your hardware can support.
Calculate the reduced ratio, approximate divider pair, output clock, and ppm error.
Copy or download the result for datasheet review or firmware configuration.

Common use cases

Choosing PLL fractional divider values for display, audio, or communication clocks.
Estimating ppm error when the exact target clock cannot be represented.
Checking baud-rate, sample-rate, or timer divider approximations.

Privacy note

Clock values and divider assumptions are processed locally. No project frequency plan is sent anywhere.

Examples

Example input

Source: 100 MHz
Target: 74.25 MHz
Max denominator: 100000

Example output

Ratio: 297 / 400
Output: 74.25 MHz
Error: 0 ppm

FAQ

Why use BigInt here?

Clock ratios can grow into large integers during reduction. BigInt avoids silent precision loss.

Does the best denominator always fit my chip?

No. Use a maximum denominator that matches the hardware register width and divider rules.

Can I use Hz instead of MHz?

Use consistent units. If both values use the same unit, the ratio remains valid.

Popular local tools

JSON to CSV JWT Decoder QR Code Workbench Base64 Encoder Regex Debugger

Go to category: Hardware Engineering Tools